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MSE Seminar Series: Daniel Josell
Friday, February 7, 2014
1:00 p.m.-2:00 p.m.
Room 2110 Chemical and Nuclear Engineering Building
For More Information:
JoAnne Kagle
301 405 5240
jkagle@umd.edu

Bottom-Up Metal Deposition for Feature Filling and Interconnect Fabrication

Daniel Josell
Staff Scientist
Metallurgy Division
Material Measurement Laboratory
NIST

I will describe deposition processes in patterned features such that filling starts towards the feature bottoms with deposition then proceeding upward. The processes, referred to as “superfill”, “superconformal” or “extreme” bottom-up filling, permit defect-free and void-free metal filling of high aspect ratio features. Their implementation using copper for sub-micrometer interconnects underlies modern high speed microelectronics. I will detail superfilling electrodeposition processes for copper, silver, and gold, along the way explaining the “Curvature Enhanced Accelerator Coverage” (CEAC) mechanism that underlies all. My talk will range from noble metals to ferrous metals and from Damascene trenches just tens of nanometers in size to Through Silicon Vias that are tens of micrometers in size. For Through Silicon Vias I will detail the very different process and underlying mechanism. For all I will show how measurements on planar substrates yield the information required to quantitatively predict all temporal and geometrical aspects of the feature filling. 

About The Speaker

Dr. Josell graduated from Harvard College in 1987 and obtained his Ph.D in Materials Science in 1992 from Harvard University. He has been a staff member of the National Institute of Standards and Technology for 20 years; he led the Thin Film and Nanostructure Processing Group from 2005 until 2012 and was Deputy Chief of the Metallurgy Division from 2006 through 2010.  He was the 2011 recipient of the Samuel Wesley Stratton Award, NIST’s highest award for scientific achievement, named after the first director of the Institute (then called the National Bureau of Standards), and is also a recipient of the highest award of the United States Department of Commerce (the Gold Medal award) for his research in superfilling processes for fabrication of damascene interconnects. He has also received the Federal Laboratory Consortium Award for Excellence in Technology Transfer for work on solder interconnect geometries.

In addition to his work on damascene interconnects in microelectronics, he has explored the mechanical and thermal transport properties of multilayered materials, the thermodynamics of interfaces, and the stability of nanoscale materials and structures and materials and processes. For the last several years his work has focused on three-dimensionally structured photovoltaic devices. He is author of more than one hundred technical publications that are, together, cited over 3000 times in the technical and patent literature and holds a patent related to interconnect fabrication.

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